The present invention relates to electric devices, and more particularly to amplifiers.
FIG. 1 is a circuit diagram of one column of an array of four-transistor memory cells in a static random access memory. For simplicity, only one memory cell 110 is shown. Four-transistor memory cells are described, for example, in the aforementioned application Ser. No. 07/709,924 entitled "Static Memories and Methods of Reading Static Memories". In one example, voltage VCC is 5.0 V and voltage VSS is 0.0 V.
Bit lines BL and BL are biased statically near 2.5 V. When memory cell 110 is read, the row-address decoder ("X-decoder", not shown) drives a word line WL high. Pass transistors 130 and 134 turn on. Depending on the state of memory cell 110, one of bit lines BL and BL is pulled up and the other one is pulled down. The column decoder ("Y-decoder", not shown) drives line 140 high (5.0 V), turning on NMOS transistors 142 and 144. A high bandwidth, low gain pre-amplifier 150 amplifies the differential voltage on bit lines BL and BL. The output of pre-amplifier 150 is connected to an input 154 of a sense amplifier 160. Sense amplifier 160 provides a CMOS level signal on its output 170.
FIG. 2 shows a circuit diagram of sense amplifier 160. PMOS transistors 210 and 212 and NMOS transistors 214, 216, 218 and 220 are connected as in a six-transistor memory cell. Six-transistor memory cells are described generally in C. A. Holt, Electronic Circuits (John Wiley & Sons, 1978), pages 293, 294. During a tracking stage, signal SENSE is low, and accordingly SENSE is high. Transistors 218 and 220 are on. Node 230 tracks the voltage on input 154 and thus charges to a value either above or below 2.5 V. A terminal 236 is biased statically at 2.5 V, so node 240 charges to 2.5 V. Transistors 250 and 252 are off isolating voltages VCC and VSS from nodes 230 and 240. If voltages VCC and VSS were made available to nodes 230 and 240, the regenerative effect would force nodes 230 and 240 to a stable state driving one node to 5.0 V and the other node to 0.0 V, and the input signal 154 would be unable to overcome the stable state.
Then signal SENSE becomes high. Transistors 218 and 220 turn off, and transistors 250 and 252 turn on. If node 230 is below 2.5 V, then it is pulled down to 0.0 V, node 240 is pulled up to 5.0 V, and NAND gate 270 provides 0.0 V on output 170. Conversely, if node 230 is above 2.5 V, gate 270 provides 5.0 V on output 170.
NAND gates 270 and 272 are provided to avoid oscillation on output 170 and a complementary output 274 during the tracking stage when nodes 230 and 240 are near 2.5 V.
It is desirable to provide a simpler sense amplifier that uses less power.